PART14Sequential Logic Circuit

Experiment Purpose

• 1.Understand the operation principle and characteristic of RS flip-flop and JK flip-flop through experiment.
• 2.Investigate the operation principle and design of counter and shift register.

Experiment 1 :RS Flip-Flop

Theory

RS flip-flop is an asynchronous sequential logic circuit(Circuit-1 of M14). By adding a gate to the input of basic circuit, it can be made that the flip-flop can response within one clock pulse(CP) occurrence period. The clock part RS flip-flop in fig.14-2(a) is composed of basic NOR flip-flop and 2 AND gates. The output of two AND gates is maintained as “0” when the CP becomes “0”, regardless of the input value of S and R. And only during the CP becomes 1 is the information permitted to reach RS flip-flop from S and R input. The clock part RS flip-flop becomes Q=1 when S=1, R=0 and CP=1, and this status is called set status. In this status, the Q value does not change even though CP=0. Also, when S=0, R=1, if CP=1, then Q=0, and this status is called clear status. Also, Q value does not change even though CP=0. One thing to noteworthy here is when S=1, R=1, CP=1. Here, Q= Q =0. At the next moment, if CP=0, the status of flip-flop becomes negative status. That is, depending on which is maintained as 1 longer among set input and reset input of RS flip-flop at the falling edge of the pulse, Q becomes “0” or “1”. This is the problem to be solved for clock part RS flip-flop. When S=0, R=0, if CP=1, Q maintains the previous status. That is, if “1” is output, Q=1, and if “0” is output, Q=0. Also, Q value does not change even though CP=0.

The symbol of Clock part RS flip-flop is as fig.14-2(b) and it has S, R, and CP as input. The CP input is expressed as a small triangle so it is not written within the quadrangle. This triangle is a symbol called dynamic indicator, and it means that the flip-flop responds when the input CP changes from low potential(0) to high potential(1) (). The output of flip-flop is expressed within the quadrangle as Q and Q. Even though Q is written within the quadrangle, other names of variables can be allocated to the flip-flop. In this case, the chosen name of variable is expressed outside the quadrangle following the output line. The status of one flip-flop is determined by the Q value under normal output. In order to get the complement(opposite polarity) of normal output, it can be earned from the output Q without inserting an inverter to the output.

Fig.14-2 (c) is a characteristic table of the flip-flop. This table summarizes the operation of flip-flop. Q is the binary status(also called current status) within given time and S and R columns indicate the possible input value. Q(t+1) is the status of flip-flop after one CP is generated(also called next status).

The characteristic equation of flip-flop is induced at Karnaugh map in fig.14-2(b). This equation expresses the value of next status with the function of current status and input. In the map, two negative status can be either “0” or “1” so is expressed as X. The relational expression SR=0 means that S and R cannot become “1” at the same time, so it should be included as part of characteristic equation.

Experiment Process

1. In Circuit-1 of M14, connect between 1c-1e, 1d-1f and compose RS flip-flop as fig.14-3.

2. Express the status when the input switch is on as 1, and when it is off as 0. Express the status when output LED is on as Output 1, when it is off as Output 0.

3. Apply the input of R, S according to table 14-1, and record the output of Q, Q following the lighting of LED-1, LED-2.

tab1 print